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DM93S41 4-Bit Arithmetic Logic Unit
October 1988 Revised May 2000
DM93S41 4-Bit Arithmetic Logic Unit
General Description
The DM93S41 4-bit arithmetic logic units can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations; the Add and Subtract modes are the most important.
Ordering Code:
Order Number DM93S41N Package Number N24A Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
Logic Symbols
Active LOW Operands
Connection Diagram
Active HIGH Operands
Pin Descriptions
Pin Name A0-A3, B0-B3 S0-S3 M Cn F0-F3 A=B G P Cn+4 Description Operand Inputs (Active LOW) Function Select Inputs Mode Control Input Carry Input Function Outputs (Active LOW) Comparator Output Carry Generate Output (Active LOW) Carry Propagate Output (Active LOW) Carry Output
(c) 2000 Fairchild Semiconductor Corporation
DS009805
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DM93S41
Functional Description
The DM93S41 is a 4-bit high speed parallel arithmetic logic unit (ALU). Controlled by the four Function Select inputs (S0-S3) and the Mode Control input (M), it can perform all the 16 possible operations or 16 different arithmetic operations on active HIGH or active LOW operands. The Function Table below lists these operations. When the Mode Control input (M) is HIGH, all internal carries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode Control input is LOW, the carries are enabled and the device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the Cn+4 output, or for carry lookahead between packages using the signals P (Carry Propagate) and G (Carry Generate). P and G are not affected by carry in. When speed requirements are not stringent, the DM93S41 can be used in a simple ripple carry mode by connecting the Carry output (Cn+4) signal to the Carry input (Cn) of the next unit. For super high speed operation the Schottky DM93S41 should be used in conjunction with the '42 carry lookahead circuit. The A = B output from the DM93S41 goes HIGH when all four Fn outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the subtract mode. The A = B output is open-collector and can be wiredAND with the other A = B outputs to give a comparison for more than four bits. The A = B signal can also be used with the Cn+4 signal to indicate A > B and A < B. The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied. Because subtraction is actually performed by complementary addition (1s complement), a carry out means borrow; thus a carry is generated when there is no underflow and no carry is generated when there is underflow. As indicated the '41 can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the operations that are performed to the operands labeled inside the logic symbol.
Function Table
Mode Select Inputs S3 L L L L L L L L H H H H H H H H S2 L L L L H H H H L L L L H H H H S1 L L H H L L H H L L H H L L H H S0 L H L H L H L H L H L H L H L H A AB A+B Logic 1 A+B B AB A+B AB AB B A+B Logic 0 AB AB A (M = H) Active LOW Inputs & Outputs Logic Arithmetic (Note 2) (M = L) (Cn = L) A minus 1 AB minus 1 AB minus 1 minus 1 A plus (A + B) AB plus (A + B) A minus B minus 1 A+B A plus (A + B) A plus B AB plus (A + B) A+B A plus A (Note 1) AB plus A AB minus A A A A+B AB Logic 0 AB B AB AB A+B AB B AB Logic 1 A+B A+B A (M = H) A A+B A+B minus 1 A plus AB (A +B) plus AB A minus B minus 1 AB minus 1 A plus AB A plus B (A + B) plus AB AB minus 1 A plus A (Note 1) (A + B) plus A (A + B) plus A A minus 1 Active HIGH Inputs & Outputs Logic Arithmetic (Note 2) (M = L) (Cn = H)
H = HIGH Voltage Level L = LOW Voltage Level Note 1: Each bit is shifted to the next more significant position Note 2: Arithmetic operations expressed in 2s complement notation
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DM93S41
TABLE 1. SUM MODE TEST Function Inputs: S0 = S3 = 4.5V, S1 = S2 = M = 0V Input Symbol Under Test tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL Ai Bi Ai Bi A B A B A B Cn Other Input Same Bit Apply 4.5V Bi Ai Bi Ai B A None None None None None Apply GND None None None None None None B A B A None Apply 4.5V Remaining A to B Remaining A to B Cn Cn None None Remaining B Remaining B Remaining B Remaining B All A Other Data Input Apply GND Cn Cn Remaining A and B Remaining A and B Remaining A and B, Cn Remaining A and B, Cn Remaining A, Cn Remaining A, Cn Remaining A, Cn Remaining A, Cn All B Output Under Test Fi Fi Fi + 1 Fi + 1 P P G G Cn + 4 Cn + 4 Any F or Cn + 4
TABLE 2. DIFF MODE TEST Function Inputs: S1 = S2 = 4.5V,S0 = S3 = M = 0V Input Symbol Under Test tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL A B Ai Bi A B A B A B A B Cn Other Input Same Bit Apply 4.5V None A None Ai None A B None None A B None None Apply GND B None Bi None B None None A B None None A None Apply 4.5V Remaining A Remaining A Remaining B, Cn Remaining B, Cn None None None None Remaining A Remaining A None None All A and B Other Data Inputs Apply GND Remaining B, Cn Remaining B, Cn Remaining A Remaining A Remaining A and B, Cn Remaining A and B, Cn Remaining A and B, Cn Remaining A and B, Cn Remaining B, Cn Remaining B, Cn Remaining A and B, Cn Remaining A and B, Cn None Output Under Test Fi Fi Fi + 1 Fi + 1 P P G G A=B A=B Cn + 4 Cn + 4 Cn + 4
TABLE 3. LOGIC MODE TEST Function Inputs: S1 = S2 = M = 4.5V, S0 = S3 = 0V Input Symbol Under Test tPLH, tPHL tPLH, tPHL A B Other Input Same Bit Apply 4.5V B A Apply GND None None Apply 4.5V None None Other Data Inputs Apply GND Remaining A and B, Cn Remaining A and B, Cn Output Under Test Any F Any F
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DM93S41
Logic Diagram
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DM93S41
Absolute Maximum Ratings(Note 3)
Supply Voltage Input Voltage: Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0C to +70C -65C to +150C
Note 3: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 -1 20 70 Nom 5 Max 5.25 Units V V V mA mA C
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIH IIL IOS ICCL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions VCC = Min, II = - 18 mA VCC = Min, IOH = Max VIL = Max VCC = Min, IOL = Max VIH = Min VCC = Max, VI = 5.5V VCC = Max, VI = 2.7V VCC = Max, VI = 0.5V VCC = Max (Note 5) VCC = Max M, S0-S3 = 4.5V All Other Inputs = 0V ICCH Supply Current VCC = Max Cn, B0-B3 = GND All Other Inputs = 4.5V
Note 4: All typicals are at VCC = 5V, TA = 25C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Min
Typ (Note 4)
Max -1.2
Units V V
2.7
3.4 0.35 0.5 1 50 -1.6
V mA A mA mA mA
-40
-100 150
140
mA
5
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DM93S41
Switching Characteristics
VCC = +5.0V, TA = +25C CL = 15 pF Symbol Parameter M = GND M = GND M, S1, S2 = GND S0, S3 = 4.5V M, S0, S3 = GND S1, S2 = 4.5V M, S1, S2 = GND S0, S3 = 4.5V M, S0, S3 = GND S1, S2 = 4.5V M, S1, S3 = GND S0, S3 = 4.5V M, S0, S3 = GND S1, S2 = 4.5V M, S1, S2 = GND S0, S3 = 4.5V M, S0, S3 = GND S1, S2 = 4.5V M = 4.5V M, S1, S2 = GND S0, S3 = 4.5V M, S0, S3 = GND S1, S2 = 4.5V M, S0, S3 = GND S1, S2 = 4.5V RL = 400 to 5.0V Conditions RL = 280 Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay Cn to Cn + 4 Propagation Delay Cn to F Propagation Delay An or Bn to G Propagation Delay An or Bn to G Propagation Delay An or Bn to P Propagation Delay An or Bn to P Propagation Delay Ai or Bi to Fi Propagation Delay Ai or Bi to Fi Propagation Delay Ai or Bi to Fi + 1 Propagation Delay Ai or Bi to Fi + 1 Propagation Delay An or Bn to F Propagation Delay An or Bn to Cn + 1 Propagation Delay An or Bn to Cn + 1 Propagation Delay An or Bn to A = B Max 12 12 12 12 14 14 15 15 14 14 15 15 20 20 21 21 24 24 25 25 20 20 18.5 18.5 23 23 23 23 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
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DM93S41 4-Bit Arithmetic Logic Unit
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide Package Number N24A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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